Field of the Invention
The present invention generally relates to a testing device and a testing method. More particularly, the present invention relates to a testing device and a testing method for memory packages.
Description of Related Art
After IC fabrication, wafer acceptance test (WAT), chip probing (CP), and package assembly, an appropriate tester should be adopted to perform final tests (FT) on the electrical functions of memory devices. Generally speaking, the highest testing frequency provided by a tester is fixed. However, the operation frequency of memory devices continuously increases, which makes existing testers not be able to test high-frequency memory devices in the next generation. A conventional method of frequency multiplication is proposed by changing a circuit board interface, or so-called Device Specific Adapter (DSA). As such, two input/output (I/O) terminals of a tester are connected to one pin of the circuit board interface to achieve frequency multiplication purpose. However, the testing efficiency and throughput may be greatly reduced. Moreover, testing accuracy is greatly reduced and potential errors are found when a single high-frequency testing signal is compared to a testing signal that has gone through frequency multiplication.
Referring to FIG. 1, a conventional memory testing device 10 includes a test head 11, a circuit board interface 12 and a socket group 13. The test head 11 includes a plurality of I/O terminals from IO0 to IO7 to output a plurality of testing signals respectively. The circuit board interface 12 is disposed between the test head 11 and the socket group 13. The circuit board interface 12 includes a plurality of buses 12a connecting the I/O terminals IO0 to IO7 to the corresponding pins of the socket group 13. The socket group 13 includes a plurality of sockets 13a to accommodate and to test a plurality of memory packages to be tested respectively. Each memory package includes one or multiple chips 200 assembled therein. The testing signals outputted from the I/O terminals IO0 to IO7 of the test head 11 are transmitted to the chips 200 of the memory package in the sockets 13a through the buses 12a. After receiving the testing signals, the chips 200 of the memory packages may transmit a plurality of feedback signals back to the test head 11. As such, the test head 11 may correlate the testing signals with the feedback signals to determine whether the chips 200 of the memory packages function normally or not.
Referring to FIG. 1 again, in the testing device 10, the frequency of the testing signals provided by the test head 11 needs to match with the operation frequency of the chips 200 of the memory packages. For example, the test head 11 with 800 Mbps read/write capability can only test the 800 Mbps chips 200 of the memory packages. Therefore, referring to FIG. 2, in the conventional testing technology, when a test head 11 with 800 Mbps read/write capability is adopted to test a 1600 Mbps chip 200 of the memory package, the original circuit board interface 12 has to be replaced by another circuit board interface 14. The circuit board interface 14 includes a plurality of first buses 14a and a plurality of second buses 14b. Therein, one of first buses 14a and the corresponding second bus 14b in pairs are connected to the corresponding pins of the half of the sockets 13a of the socket group 13 to achieve frequency multiplication effect. However, the other half of the sockets 13a are idle contacts. Therefore, the chip 200 of the memory package can be tested through transmitting two testing signals from two corresponding I/O terminals IO0 to IO3 and IO4 to IO7 to one corresponding pin of the socket group 13. The testing method is able to test memory packages with higher frequency by the test head 11 with lower frequency. Nevertheless, the number of the memory packages which can be tested by the test head 11 is reduced to half, which leads to lower tester utilization and lower testing throughput. Moreover, referring to FIG. 2 again, in the conventional testing technology, when two testing signals with a timing difference transmit from two corresponding I/O terminals IOU to IO3 and IO4 to IO7 are connected to a corresponding one of the pins DQ0 to DQ3, the connecting lengths of the first buses 14a and the second buses 14b are different, which causes timing errors. As such, the pins DQ0 to DQ3 of the socket group 13 may not accurately receive two testing signals and merge into one double-frequency testing signal, and the time delay between the two testing signals would lead to input/output errors of the double-frequency testing signal.